Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications

A run-time reconfigurable multiply-accumulate (MAC) architecture is introduced. It can be easily reconfigured to trade bitwidth for array size (thus maximizing the utilization of available hardware); process signed-magnitude, unsigned or 2’s complement data; make use of part of its structure or adapt its structure based on the specified throughput requirements and the anticipated computational load. The proposed architecture consists of a reconfigurable multiplier, a reconfigurable adder, an accumulation unit, and two units for data representation conversion and incoming and outgoing data stream transfer. Reconfiguration can be done dynamically by using only a few control bits and the main component modules can operate independently from each other. 1 This work was partially supported by the project AMDREL IST-2001-34379 funded by EC.